1. Field of Invention
This invention relates to a multi-chips module assembly package. More particularly, the present invention is related to a multi-chips module assembly package having an intermediate substrate with a via, wherein the via has a plurality of electrically conductive layers formed therein and electrically isolated from each other.
2. Related Art
Recently, integrated circuit (chip) packaging technology is becoming a limiting factor for the development in packaged integrated circuits of higher performance. Semiconductor package designers are struggling to keep pace with the increase in pin count, size limitations, low profile, and other evolving requirements for packaging and mounting integrated circuits.
Due to the assembly package in miniature and the integrated circuits operation in high frequency, MCM (multi-chips module) package is commonly used in said assembly package and electronic devices. Usually, said MCM package mainly comprises at least two chips encapsulated therein, for example a processor unit, a memory unit and related logic units, so as to upgrade the electrical performance of said assembly package. In addition, the electrical paths between the chips in said MCM package are short so as to reduce the signal delay and save the reading and writing time.
Generally speaking, as shown in FIG. 1, it illustrates the cross-sectional view of a conventional assembly package in a side-by-side type. Two assembly packages 11 and 12 are disposed on a carrier 13, for example an organic substrate, in parallel, and electrically connected to an outer device through conductive devices 14, for example, solder balls. Moreover, said multi-chips module assembly package (MCM assembly package) can be an assembly package in a stacked type as shown in FIG. 2 or an assembly package with an intermediate substrate 20 therein as shown in FIG. 3.
As shown in FIG. 2, a first assembly package 21 comprises a first substrate 211 and a first chip 212, wherein the first chip 212 is flip-chip bonded to and electrically connected to the first substrate 211; and a second assembly package 22 comprises a second substrate 221 and a second chip 222 which is flip-chip bonded to and electrically connected to the second substrate 221. Therein, the first package 21 and the second package 22 can also be wire-bond packages. In addition, the first package 21 further comprises a first conductive device 213, for example a solder ball, mounted on the lower surface of the first substrate 221 to electrically connect to the second package 22 through the second substrate 221. Similarly, said second package 22 further comprises a second conductive device 223 formed on the lower surface of the second substrate 221 to transmit the signals from the first package 21 and the second package 22 to an external device. The second chip 222 is disposed below the lower surface of the first substrate 211, so there is not enough space to dispose the first conductive devices 213 on the lower surface of the first substrate 211. Accordingly, the number of the first conductive devices 213 will be reduced.
Next, referring to FIG. 3 and FIG. 4, which illustrate another stacked-type assembly packages. It should be noted that the reference numeral of each element in FIGS. 3 and 4 corresponds to the same reference numeral of each element in FIG. 2. There is an opening 206 formed in an intermediate substrate 20; the second chip 222 of the second package 22 is disposed in the opening 206 and electrically connected to the first package 21. Therein, the first package 21 comprises a first conductive device 213, for example a solder ball, formed on the lower surface of the first substrate 211 to electrically connect to the intermediate substrate 20, and the lower surface of the intermediate substrate 20 has a third conductive device 23 formed thereon to electrically connect to the second package 22. In addition, said second package 22 further comprises a second conductive device 223 formed on the lower surface of the second substrate 221 to transmit the signals from the first package 21 and the second package 22 to an external device through the intermediate substrate 20.
As shown in FIG. 5, the intermediate substrate 20 mainly includes a board 200. The board 200 comprises a core board 201, a plurality of insulating layers 202 and circuit layers 203. The insulating layers 202 and the circuit layers 203 are interlaced with each other. The circuit layers 203 are electrically connected with each other through vias 204 such as through holes, buried vias or blind vias. Now taken a through hole for example, initially, the insulating layers 202 and the circuit layers 203, which are interlaced with each other, are penetrated to form a through hole therein by the method of mechanical drilling or laser ablation. Next, the inner wall of the through hole is electro-less plated with a copper film and then another copper layer is deposited on the copper film. Finally, the through hole is filled with an insulating material or an insulator, for example epoxy and ink. Now referring to FIG. 6, via land 205 is disposed at the periphery of the via 204 to electrically connect the circuit traces 203 and the via 204. Generally speaking, if the diameter of the via 204 is about 300 μm, the diameter of the via land 205 will be about 500 μm. In addition, a landless design can be employed to save the area for the arrangement of the via land 205. However, the process of the landless design is complex and the cost is increased.
As shown in FIG. 6, the via lands 205 occupy a lot of areas so that the areas for laying out the circuit traces are reduced. In such a manner, the circuit traces 203 will be finer and the pitches between the circuit traces 203 will be fined down. Consequently, it will be difficult to fabricate this kind of intermediate substrate. Besides, the quality of the electricity will be seriously affected in that, with reference to FIG. 6, the bent portions of the conductive traces and the distance of the signal transmission are increased.
Moreover, referring to FIG. 3, said intermediate substrate 20 is provided to define a space so as to prevent the second chip 222 of the second package 22 from interfering the first substrate 211 being disposed above said second chip 222. However, the first conductive device 213 can only be disposed at the periphery of the lower surface of the first substrate 211, so the number of the first conductive devices to be mounted on the first substrate 211 is decreased. If the number of the vias 204 is increased by utilizing plasma, Nd:YAG laser and excimer laser to reduce the size of the via 204, the areas for laying out the circuit traces 203a can be increased to reduce the bent portions of the circuit traces 203a. However, the fabrication method of plating metal layer on the inner wall of the via 240 will become more complex due to the smaller diameter of the via 240. In addition, the via lands 205 occupy a great portion of the circuit layers 204, so the bent portions of the circuit traces 203a are increased and the distance for transmitting signals are extended.
Therefore, providing another assembly package to solve the mentioned-above disadvantages is the most important task in this invention.